Automatic frequency control for differentially coherent phase detection

ABSTRACT

Automatic frequency control apparatus is provided for controlling the carrier frequency of a differentially coherent phase-shift keyed (DC-PSK) carrier signal. More particularly, the binary signal carried via the DC-PSK carrier signal, after recovery therefrom, is multiplied by the output signal from a quadrature differential phase detector to generate a product signal which, when averaged, has polarities which are indicative of whether the carrier frequency has increase or decreased from a preselected value. The generated product signal thus can be used as an error control signal for maintaining the carrier frequency at such preselected value.

United States Patent [111 3,911,219

Mullins 1 Oct. 7, 1975 AUTOMATIC FREQUENCY CONTROL FOR Primary ExaminerBenedict V. Safourek DIFFERENTIALLY COHERENT PHASE Attorney, Agent, or Firm-John J. Torrente; John K. DETECTION Mullarney [75] Inventor: Joe Hill Mullins, Fair Haven, NJ.

[73] Assignee: Bell Telephone Laboratories,

Incorporated, Murray Hill, NJ. Automatic frequency control apparatus is provided for controllin the carrier fre uency of a differential] co- [22] Flled: 1974 herent plfase-shift keyed (DC-PSK) carrier signal. [21] App]. No.: 450,090 More particularly, the binary signal carried via the DC-PSK carrier signal, after recovery therefrom, is multiplied by the output signal from a quadrature dif- [57] ABSTRACT [52] f 3 4 32 ferential phase detector to generate a product signal [51] 178/67 525/320 346 which, when averaged, has polarities which are indica- [58] do g i 12 tive of whether the carrier frequency has increase or g decreased from a preselected value. The generated product si nal thus can be used as an error control si g g References Cited glglllegoerdnlzlilnutgining the carrier frequency at such pre UNITED STATES PATENTS 3,479,600 10/1969 Miller 325/423 11 Claims, 1 i g Figures 3,638,125 1/1972 Goell 3,808,541 4/1974 Baker et a1. 325/346 D|FER EIflIl PHiSE-DETECTOR |4- I 1 I l6 1 I "I I 15 u i I DOWN CONVERTED mcomme DC-PSK SIGNAL s Dow W SIGNAL CONVERTER I3 os tf L L AreR I 2| L VOLTAGE CONJORCIKLLLED kgl ERROR SIGNAL e 20 I I OSCILLATOR F'LTER f QUADRATURE DIFFERENTIAL E A E l b L' AVERAGED I [g ERROR I CONTROL SIGNAL I I AVG i I dq I I I I I I US. Patent 0a. 7,1975 Sheet 2 of 4 3,911,219

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U.S. Patent Oct. 7,1975 Sheet 3 Of4 3,911,219

A: $55G M 8 :81; N muzmfita u E m1: 1? we 1n C E Ac c v u 0 6t 1| 1 \\/\l./\|( L o -l|1||l\ A 15 X153 5 S S E P T q A m .1 T J 0 m 6Q AUTOMATIC FREQUENCY CONTROL FOR DIFFERENTIALLY COHERENT PHASE DETECTION BACKGROUND OF THE INVENTION This invention relates to data communications and, in particular, to apparatus for providing automatic frequency control in the differential detection of phaseshift keyed signals.

It has become well known in the communications art to employ phase-shift keying techniques to transmit a binary signal. In one such technique, generally referred to as differentially coherent phase-shift keying (DC- PSK), each of the two states of the binary signal is encoded into a phase difference between the oscillations of a carrier occurring during successive or adjacent T second time intervals. In a typical case, a phase difference between the carrier oscillations during adjacent T second time intervals will correspond to the encoded form of one state (i.e., the state) of the binary signal, while a 180 phase difference will correspond to the encoded form of the other state (i.e., the state) of the signal.

It can be appreciated that when employing a DC-PSK signal to transmit a binary signal, suitable detection apparatus must be provided at the system receiver in order to properly convert the transmitted differential phase-shifts into their corresponding binary states. In particular, such receiver detection apparatus generally comprises a down converter which down converts the carrier frequency of the received DCPSK signal to a preselected intermediate frequency level by mixing it with a locally generated oscillator signal. The resultant down converted DC-PSK signal is then applied to a differential phase signal detector which compares the phase of the signal with that of a replica of the signal which has been delayed by one T second time interval. From such comparison the phase detector generates an output analog signal which is a measure of the phase difference between the carrier oscillations occurring during adjacent T second time intervals and, hence, an output analog signal which is a direct measure of the encoded binary signal.

More specifically, during each T second interval in which the carrier oscillations of the signal and delayed replica thereof are in-phase, the phase detector develops an output signal of one polarity (e.g., a positive polarity) which is indicative of the transmission of one state (the state) of the binary signal, while during each T second interval in which such oscillations are out of phase, the detector develops an output signal of opposite polarity (i.e., of negative polarity) which is indicative of the transmission of the other state (the state) of the binary signal. To fully recover the binary signal, the aforesaid analog output signal is then applied to a sampling circuit which samples the signal at the midpoint of each T second time interval and generates an output pulse for each sample having a polarity equivalent to that of the sample and an amplitude and duration of uniform height and length.

While the abovedescribed basic detection apparatus at the system receiver does provide adequate recovery of the binary signal when the carrier frequency of the down converted DC-PSK signal remains substantially unchanged, such is not the case when the carrier frequency varies due to drifts in the incoming carrier frequency and/or the frequency of the local oscillator. In

the latter cases, the occurrence of variations in the carrier frequency of the down converted DC-PSK signal results in the generation of spurious responses which cause errors in the recovered binary signal. To avoid such spurious responses, it is thus necessary to control the carrier frequency of the down converted DC-PSK signal so it remains locked to its preselected intermediate frequency value. Unfortunately, however, in situations where the DC-PSK signal is broadband, conventional techniques for providing automatic frequency control of the carrier frequency have been found to be unacceptable.

It is thus a broad object of the present invention to provide suitable apparatus at the system receiver for controlling the carrier frequency of a received DC-PSK carrier signal.

SUMMARY OF THE INVENTION In accordance with the principles of the present invention, automatic frequency control of the carrier frequency of a down converted DC-PSK signal is provided by multiplying the binary signal recovered from the DC-PSK signal with the output signal from a quadrature differential phase detector to develop an error control signal which is of substantially one polarity during an increase of the carrier frequency from its preselected intermediate frequency value and of substantially the opposite polarity during a decrease of the carrier frequency from such value. This aforesaid error control signal, after being averaged, is then applied to the local oscillator feeding the receiver down converter such that said one polarity of the averaged error signal, which polarity is indicative of an increase in the carrier frequency from its preselected value, causes a commensurate change in the local oscillator frequency, thereby decreasing the carrier frequency toward such value, and so that said opposite polarity of the averaged error signal, which polarity is indicative of a decrease in the carrier frequency from its preselected value, causes a commensurate change in the local oscillator frequency, thereby increasing the carrier frequency also toward such preselected value.

More particularly, the quadrature differential phase detector functions to compare the down converted DC- PSK signal with a replica of itself which has been delayed by a T second interval plug From such comparison, the detector develops an output analog signal whose polarity during a substantial portion of the duration of each pulse of the recovered binary signal is either the same as or opposite to the polarity of such pulse, depending upon whether the carrier frequency of the DC-PSK signal has increased or decreased from its preselected value. As a result, the output analog signal is always of substantially the same polarity as the recovered binary signal for one type of change of the carrier frequency relative to its preselected value (e.g., an increase in the carrier frequency therefrom) and always of substantially the opposite polarity for the opposite type change (a decrease, in the case of the aforesaid example) of the carrier frequency from such value. Multiplication of the aforesaid output analog signal and the recovered binary signal thus results in a product signal having substantially one polarity during such an increase in frequency of the carrier and substantially an opposite polarity during such a decrease in frequency of the carrier. The aforesaid product signal, hence, when averaged, has said one polarity during an increase of the DC-PSK carrier frequency from its preselected value and said opposite polarity during a decrease of the carrier from such value and, as a result, as above indicated, can be employed as an error control signal to restore the carrier to such preselected value.

DESCRIPTION OF THE DRAWINGS The above and other features and aspects of the present invention will become more apparent upon consideration of the following detailed description taken in conjunction with the following drawings in which:

FIG. 1 shows an automatic frequency control arrangement in accordance with the principles of the present invention;

FIGS. 2-9 illustrate the signals appearing at various points in the arrangement of FIG. 1;

FIG. shows a circuit arrangement which can be employed to perform the function of the quadrature differential phase detector included in the apparatus of FIG. 1; and

FIGS. 11-16 illustrate the signals appearing at various points in the circuit of FIG. 10.

DETAILED DESCRIPTION FIG. 1 shows, in block diagram form, an apparatus 1 1 for use in the receiver of a transmission system which transmits binary information via a DC-PSK signal s which comprises a carrier at a carrier frequency w, More particularly, apparatus 11 includes a down converted 12 which is fed the incoming DC-PSK signal s and an oscillator signal v which is developed by a voltage controlled oscillator (\/CO) 13. Down converter 12 mixes or multiplies the signals s and v to develop a DC-PSK signal s, at the difference or intermediate fre quency W' The incoming DC-PSK signal s carries the binary signal being transmitted via the phase difference between its carrier oscillations occurring during successive or adjacent T second time intervals, where the time T is a function of the information rate of the binary signal. The aforesaid down conversion of the signal s to the signal s by down converter 12 must thus result in a carrier frequency wi for S which preserves the phase relationship between the aforementioned signal oscillations. As a result, the frequency w,, of local oscillator signal v is initially set so that such a carrier frequency for s, is developed, i.e., is set so that the carrier frequency w,- (w w,,) of .9 is made equal to w In FIG. 2, the down converted DC-PSK signal s at the carrier frequency W is illustrated. 5 T second intervals, labelled O-5, of the signal s are shown. As depicted, each such interval comprises an integer number of cycles (shown, illustatively, as 4 cycles) of the carrier w As above-indicated, the phase difference between the carrier oscillations of s occurring during each set of successive or adjacent T second intervals represents the encoded form of a transmitted state of the transmitted binary signal. Thus, in FIG. 2, the differences in phase between the oscillations of s during the sets of adjacent intervals O-l l-2, 2-3 and 3-4 represent four transmitted states of the binary signal, the aforesaid four states being those occurring during the time intervals l, 2, 3 and 4.

As can be observed from FIG. 2, the carrier oscillations of s during the sets of adjacent intervals 0-1 and 3-4 are illustrated as having a 0 phase difference,

while those during the sets of adjacent intervals l-2 and 2-3 are illustrated as having a phase difference. For purposes of discussion, it will be assumed that a 0 phase difference between the carrier oscillations of s represents the encoded form of a state of the binary signal and a 180 phase difference the encoded form of a state of the signal. Hence, the illus trated intervals of signal 5 represent the four transmitted states and The DC-PSK signal 5, is coupled from down converter 12 to a conventional differential phase detector 14 which functions to develop from the signal s and analog signal d which corresponds to the binary signal being transmitted. In particular, detector 14, via delay element 15, operates to form a replica s of the signal s which is delayed by a time T relative to s Comparator 16 of the detector then acts to compare the phase of the signal s with the phase of the signal s during each of the time intervals l-4. If the phase difference between the signals during a particular interval is 0, then the output developed by the comparator is of substantially one polarity (assumed for purposes of illustration to be a positive polarity) and, if the phase difference is 180 then the output developed is of substantially the opposite polarity (i.e., a negative polarity in this case, in view of the previous assumption). It thus can be appreciated that a substantially positive polarity output from detector 14 during an interval T indicates the transmission during the interval of a state of the transmitted binary signal, while a substantially negative polarity output indicates the transmission during the interval of state of such signal.

FIGS. 3 and 4 illustrate, respectively, the delayed signal s and the detector analog output signal d resulting from comparing the phase of to s for the T second intervals l-4. As is shown, the resultant detector output during the intervals 1 and 4 is substantially positive, thereby correctly indicating transmission of a state of the binary signal during these intervals, while such output is substantially negative during the intervals 2 and 3, thereby correctly indicating transmission of a state of the binary signal during these latter two intervals.

To fully recover the binary signal, the detector analog signal d is applied to a conventional timing recovery and regenerator circuit 17. In particular, circuit 17 samples the signal d during the intervals 1-4 and from such sampling produces an output pulse during each interval of uniform duration and amplitude and of a po- Iarity identical to that of the substantially occurring p0- larity of the signal (1 during such interval. The recovered binary signal b of FIG. 5 thus results.

It can be appreciated that the ability of detector 14 and regenerator circuit 17 to correctly recover the bi nary signal being transmitted is dependent upon maintaining the carrier frequency w of the DC-PSK signal 5 at the frequency W More particularly, as aboveindicated, any departure of such carrier frequency from w due to drifts in the incoming carrier frequency w and/or the local oscillator frequency w,,, results in disturbing the phase relationship between the oscillations of S occurring during adjacent T second time intervals. Such disturbance is reflected as spurious outputs from detector 14, which outputs, in turn, cause errors to occur in the recovered binary signal b developed by regenerator 17.

In order to insure against such errors, apparatus 11 is provided with an additional automatic frequency control apparatus 18 which acts to maintain the carrier frequency of the signal S, at the frequency w More specifically, in accordance with the invention, appara tus 18 comprises a quadrature differential phase detector 19 and a multiplier or product circuit 20. As will be explained more fully hereinbelow, product circuit 20 receives the output d, of quadrature detector 19 and multiplies such output with the recovered binary signal b to develop an error control signal e which is of substantially one polarity when the carrier frequency WU of the signal 3 has increased above the frequency Wii and of substantially the opposite polarity when the carrier frequency w has decreased below w The aforesaid error signal e is then averaged, via passage through a low pass filter 21, thereby resulting in an averaged error control signal e having said one polarity and said opposite polarity, said polarities being indicative of and occurring during, respectively, the aforementioned increase and decrease in the frequency WU. The averaged error signal is then applied to the VCO 13 in typical servo loop fashion such that said one polarity of the averaged signal (assumed for illustrative purposes to be the negative polarity of the signal), which polarity is indicative of an increase in the carrier frequency above Wif as aforesaid, causes an increase in the output oscillator frequency and, thus, a decrease in the carrier frequency back toward w and such that said opposite polarity of the averaged signal, (positive polarity of the signal), which polarity is indicative of a decrease in the carrier frequency below w also as aforesaid, causes a decrease in the output oscillator frequency and, hence. an increase in the carrier frequency again back toward w As indicated, the quadrature differential phase detector 19 develops its output signal d, in response to the DS-PSK signal 5 being applied thereto. More particularly, detector 19 acts, via a delay element 22 and a 90 phase-shifter 23, to first generate a replica of the signal s which is delayed by a T second time interval plus an additional 90 relative thereto. The detector then compares the delayed signal with the signal 3 in a comparator 24 such that an output analog signal (the detector output signal d is developed which has a polarity during a substantial portion of each of the T second intervals 1-4 which is the same as or opposite to the polarity of the recovered binary signal b during such interval, depending upon whether there has been an increase or decrease in the carrier frequency WU above or below w The detector output signal d is thus always of substantially the same polarity as the recovered signal b in the case of one type of change in the carrier frequency w,-, (for example, an increase of W above w and of substantially the opposite polarity to the signal b in the case of the opposite type change in w (a decrease in w below w As a result, the product of the two signals 11,, and b is itself always of substantially one polarity during the former type of change and of substantially the opposite polarity during the latter type of change, as above-indicated.

The aforesaid result can be further illustrated by assuming that during an increase in the carrier frequency W above WiI the signal d developed by quadrature detector 19 is of substantially opposite polarity to the recovered binary signal b. This means, of course as above-discussed that the signal d developed by detector 19 will be of substantially the same polarity as the signal b for a decrease in WU below w If it is further assumed, moreover, that the carrier frequency WU- had been increased during the illustrated intervals of s then the signal 41,, developed by detector 19 during the intervals l4 would be substantially opposite polarity to the signal b, as is shown in FIG. 6. Multiplication of the signal (1,, with b thus results in error signal 2 having substantially all negative polarities, as shown in FIG. 7. As is apparent, such an error signal, when averaged, results in a negative polarity signal which, as aboveindicated, increases the frequency of VCO 13, thereby decreasing the carrier frequency back to w If, on the other hand, however, it is assumed that the carrier frequency w had been decreased below w during the illustrated intervals of s,, then the signal d developed by detector 19 during the intervals 1-4 would be of substantially the same polarity as the signal b, as shown in FIG. 8. Multiplication of the signal d,, with b in this case thus results in an error signal 6 having substantially all positive polarities, as shown in FIG. 9. As is also apparent such an error signal, when averaged, results in a positive polarity signal which, as above-indicated decreases the frequency of VCO 13, thereby increasing the carrier frequency w back to In FIG. 10, a specific circuit arrangement 101 which can be employed to perform the function of the quadrature detector 19 is illustrated. As shown, the arrangement comprises first and second 3db hybrid couplers 102 and 103 having ports a, b, c, d and a", b", c, (1'', respectively.

Port a of coupler 102 serves as the input port of the detector 101. Ports b, c and a" of coupler 102, are connected, respectively, to port a" of coupler 103, to the input end of a T second delay element 104 and to a terminating resistance 105. The output end of delay element 104 is connected, in turn, to the input end of a phase-shifter 105 whose output end is coupled to port d" of coupler 103.

The remaining two ports b" and c" of coupler 103 serve as inputs to detectors 106 and 107, respectively, each of which typically might be a square law device. The outputs of detectors 106 and 107 are, in turn, coupled through low pass filters 108 and 109, respectively, to a difference circuit 111 whose output is the desired signal d Hybrid couplers 102 and 103 are conventional couplers which couple signals applied to their a and d ports in a similar manner. In particular, a signal applied to the a port of each coupler is split equally between the b and 0 ports thereof, with the signal coupled to the b port experiencing a 0 relative phase-shift and the signal coupled to the c port a 90 relative phase-shift. Similarly, a signal applied to the d port of each coupler is split equally between the b and c ports thereof, with the signal coupled to the b port experiencing a 90 relative phase-shift and the signal to the c port a 0 relative phase-shift.

In operation, the down converted DC-PSK signal 3 is applied to a port a of coupler 102. The signal s is equally split between the ports b and c so that appearing at these ports are the signals s and s respectively, where s )/2 and s equals S shifted in phase by 90. The signal S is then coupled directly to port a, while the signal s' is delayed for a time T and phase-shifted an additional 90 in passing through elements 104 and 105, respectively, and thus arrives at port d of coupler 103 as the signal s" The signal 5 at port a" is split between the ports b" and c of coupler 103 so that appearing at these ports are the signals s and s,,,, where S (s )/2 and 3', equals 5 shifted in phase by 90. Similarly, the signal s at port d" is also split between the ports b" and c so that due to this latter signal the signal s (s )/2 appears at port and the signal 5 which is equal to s" shifted in phase by 90 appears at the port b. The total signal at port I) of coupler 93 is thus the sum signal s (s s"' while total signal at port 0 of the coupler is the sum signal S (s' s The signals s and s are then coupled from the ports b and 0 through their respective square law detectors 106 and 107 and low pass filters 108 and 109, whereby the envolopes of the signals are detected, thereby resulting in the low frequency positive polarity signals s' and s' These latter two signals are applied to the inputs of difference circuit 111 wherein they are subtracted to produce the output signal d In order to observe that the signal d,, from detector circuit 101 is equivalent to that produced by quadrature differential phase detector 19 of FIG. 1, such output will now be determined for the cases of the carrier frequency W of s being equal to, greater than and less than the desired frequency WU.

More particularly, the signals 8 and S in the intervals l-4 are plotted in FIG. 11 for the case where WU w Similarly, the signals s and s are plotted in FIG. 12 for the same case. As can be seen from these figures, when w,-,-= wthe pair of signals s, and s are out of phase by equivalent amounts (either +90 or :90) during each of the intervals l-4, as are the pair of signals s and s" Such phase relationships between the aforesaid pairs of signals cause the sum signals S and x resulting therefrom to be equivalent, each having a substantially equal amplitude and phase in each of the plotted intervals, as can be seen in FIGS. 13 and 14. The equivalence between the signals s and S in turn, causes the positive polarity output signals 1," and s' illustrated in FIGS. 15 and 16, to be of substantially equal amplitude. The subtraction of the signals s' and s,,." in difference circuit 111 thus results in a zero output for d thereby correctly indicating that W is at the desired frequency If, however, the frequency w had been increased from w during illustrated intervals, such an increase in w,-; would have resulted in shifting the signal s further to the left on the time scale relative to the signal s as is indicated by the arrow 112 in FIG. 11. As a result of such a shift, the signals 3 and 5 become more out of phase (their phase difference increases toward 180) in those intervals where the signals were +90 out of phase at WHO (the intervals 2 and 3), thereby decreasing the amplitude of the sum signal s in such intervals. In those intervals where the signals were 90 out of phase at w (the intervals 1 and 4), however, the opposite occurs. That is, the signals become more in phase (their phase difference decreases toward 0), thereby increasing the sum signal r Thus, as shown in FIG. 13, for w w the sum signal 11," has an increased amplitude in intervals 1 and 4 and a decreased amplitude in the intervals 2 and 3. This amplitude change in 5 is similarly reflected in the amplitude of the output signal s thus causing the latter signal to have an increased amplitude in intervals 1 and 4 and a decreased amplitude in intervals 2 and 3, as shown in FIG. 15.

An increase in the frequency w above w in the illustrated intervals, would likewise have resulted in shifting the signal s' further to the left on the time scale relative to the signal s as indicated by the arrow 121 in FIG. 12. As a result of such a shift, the latter two signals become more out of phase in these intervals where they were out of phase at w (the intervals l and 4) and more in phase in these intervals where they were 90 at W (the intervals 2 and 3). The resultant sum signal s and hence the output signal s' are thus both increased in amplitude in the latter two intervals and decreased in amplitude in the former two intervals, as shown in FIGS. 14 and 16.

It can be appreciated that the above-described change in the sum signals s and s g' which occurs when W is increased above w cause a corresponding change in the difference output signal d,,. In particular, assuming difference circuit 111 subtracts the sum signal s' from s it is apparent that the difference signal (1,, will have a positive polarity during a substantial portion of the intervals 2 and 3 and a negative polarity during a substantial portion of the intervals l and 4, which is precisely the indicated form of d,, shown in FIG. 6 for an increase in w,-, above w Having thus observed that detector 101 produces the proper output signal in the case of WU being increased above w the behavior of the detector will now be examined under the assumption that w had been decreased below w during the illustrated intervals of x Under such a circumstance, the signal s would have been shifted further to the right on the time scale relative to the signal s,,, as indicated by the arrow 113 in FIG. 11. As a result, in the intervals I and 4, the two signals become more out of phase, thereby causing the signals S11," and s' to be decreased in amplitude in these intervals (see FIGS. 13 and 15). In the intervals 2 and 3, however, the signals become more in phase with the result that the signals s and s,,," are increased in amplitude.

Similarly, a decrease in the frequency w below w would have caused the signal s to be shifted further to the right on the time scale relative to the signal s as indicated by the arrow 122 in FIG. 12. As a result, in the intervals 1 and 4 the two signals become more in phase and in the intervals 2 and 3 more out of phase. The resultant signals 5 and s hence, have an increased amplitude in the former intervals and a decreased amplitude in the latter intervals, as shown in FIGS. 14 and 16.

Subtraction of the signal s'n," from s' m in difference circuit 111 thus results in an output signal (1,, having a positive polarity during a substantial portion of the intervals 1 and 4 and negative polarity during a substantial portion of the intervals 2 and 3, which again is precisely the form of d,, for w decreased below w as shown in FIG. 8.

In all cases, it is understood that the above-described arrangements are merely illustrative of some of the many possible specific embodiments which represent applications of the present invention. Numerous and varied other arrangements can readily be devised in accordance with these principles without departing from the spirit and scope of the invention. For example, in

the discussion, hereinabove, it was implicitly assumed that the carrier frequency w was greater than the local oscillator frequency w However, the principles of the invention are applicable, as well, when w, w,,. In such a case, the signal e would be applied to VCO 13 so as to decrease its frequency when w increased above W and, similarly, to increase its frequency when w decreased below w Additionally, the binary signal being transmitted via the DP-PSK signal s could have been carried via other phase differences than those illustrated. Thus, for example, phase differences of +90 and -90 could have also been employed.

What is claimed is: 1. Apparatus for use in a receiver which receives a DC-PSK signal, said signal comprising a carrier at a frequency w, which provides a means for carrying first and second states of a transmitted binary signal via first and second phase differences, respectively, between the oscillations of said carrier occurring during successive T second intervals comprising oscillator means for generating an oscillating signal at a frequency w,,;

down converter means for mixing said DC-PSK signal and said oscillating signal to produce a down converted DC-PSK signal at an intermediate difference frequency W V differential phase detector means responsive to said down converted signal for recovering therefrom a recovered binary signal which corresponds to said transmitted binary signal, said recovered binary signal comprising opposing polarity pulses which correspond, respectively, to said first and second states of said transmitted binary signal;

quadrature differential phase detector means also responsive to said down converted signal for generating an output signal having a polarity during a substantial portion of the duration of each of said pulses which is the same as or opposite to the polarity of such pulse depending upon whether said frequency w is above or below a preselected frequency w means for multiplying said recovered binary signal with said output signal, thereby developing an error control signal having substantially one polarity when said frequency w is above WHO and substantially the opposite polarity when said frequency w is below w and means for applying said error control signal to said local oscillator to control said frequency w,, such that said frequency w is maintained at w 2. Apparatus in accordance with claim 1 in which:

each of said pulses is associated with a particular one of the T second intervals of said carrier, and each pulse is of one polarity if the phase difference between the carrier oscillations of its associated interval and the carrier oscillations of the immediately preceding interval is equal to said first phase difference and each is of a polarity opposite to said one polarity if the phase difference between the carrier oscillations of its associated interval and carrier oscillations of the immediately preceding interval is equal to said second phase difference;

and said output signal has a polarity during a substantial portion of each of said intervals which is the same as or opposite to polarity of the pulse associated with such interval, depending upon whether said frequency w is above or below said frequency w 3. Apparatus in accordance with claim 1 in which said means for applying includes means for averaging said error control signal.

4. Apparatus in accordance with claim 1 in which said differential phase detector means comprises:

delay means responsive to said down converted signal for producing a delayed signal which is a replica of said down converted signal and which is delayed by T seconds relative thereto;

and comparator means for comparing the phases of said delayed signal and said down converted signal.

5. Apparatus in accordance with claim 1 in which said first and second phase differences are 0 and 180, respectively.

6. Apparatus in accordance with claim 1 in which said quadrature detector means comrpises:

a delay means responsive to said down converted signal for generating a quadrature delayed signal which is a replica of said down-converted signal and which is delayed by T seconds plus relative thereto;

and means for comparing the phases of said quadrature delayed signal and said down converted signal.

7. Apparatus in accordance with claim 1 in which said quadrature detector comprises:

first and second hybrid couplers, each having first, second, third, and fourth ports, said first port of said first coupler being responsive to said down converted signal and said second port of said first coupler being connected to said first port of said second coupler;

a delay means for providing a T second plus 90 delay to signals passing therethrough, said delay means being connected between said third port of said first coupler and fourth port of said second coupler;

a difference circuit whose output comprises said output signal, said difference circuit having first and second input ports;

a first envelope detector connected between said second port of said second coupler and said first input port;

and a second envelope detector connected between said third port of said second coupler and said second input port.

8. Apparatus in accordance with claim 7 in which each of said couplers is a 3db hybrid coupler.

9. Apparatus in accordance with claim 7 in which a signal applied to the first port of each of said couplers is equally divided between said second and third ports thereof, with the portion of the signal appearing at the second port receiving a 0 relative phase shift and the portion appearing at the third port a 90 relative phaseshift;

and a signal applied to the fourth port of each of said couplers is equally divided between said second and third ports thereof, with the portion of the signal appearing at the third port receiving at 0 relative phase shift and the portion appearing at the second port a relative phase-shift.

10. Apparatus in accordance with claim 1 in which said output signal is of substantially the opposite polarity to said binary signal when WU is above W and is of substantially the same polarity as said binary signal when w is below w 11. Apparatus in accordance with claim 8 in which said error control signal is of substantially a negative polarity when w is above W and said error control signal is of substantially a positive polarity when w is below w 

1. Apparatus for use in a receiver which receives a DC-PSK signal, said signal comprising a carrier at a frequency wc which provides a means for carrying first and second states of a transmitted binary signal via first and second phase differences, respectively, between the oscillations of said carrier occurring during successive T second intervals comprising oscillator means for generating an oscillating signal at a frequency wo; down converter means for mixing said DC-PSK signal and said oscillating signal to produce a down converted DC-PSK signal at an intermediate difference frequency wif; differential phase detector means responsive to said down converted signal for recovering therefrom a recovered binary signal which corresponds to said transmitted binary signal, said recovered binary signal comprising opposing polarity pulses which correspond, respectively, to said first and second states of said transmitted binary signal; quadrature differential phase detector means also responsive to said down converted signal for generating an output signal having a polarity during a substantial portion of the duration of each of said pulses which is the same as or opposite to the polarity of such pulse depending upon whether said frequency wif is above or below a preselected frequency wif ; means for multiplying said recovered binary signal with said output signal, thereby developing an error control signal having substantially one polarity when said frequency wif is above wif and substantially the opposite polarity when said frequency wif is below wif ; and means for applying said error control signal to said local oscillator to control said frequency wo such that said frequency wif is maintained at wif .
 2. Apparatus in accordance with claim 1 in which: each of said pulses is associated with a particular one of the T second intervals of said carrier, and each pulse is of one polarity if the phase difference between the carrier oscillations of its associated interval and the carrIer oscillations of the immediately preceding interval is equal to said first phase difference and each is of a polarity opposite to said one polarity if the phase difference between the carrier oscillations of its associated interval and carrier oscillations of the immediately preceding interval is equal to said second phase difference; and said output signal has a polarity during a substantial portion of each of said intervals which is the same as or opposite to polarity of the pulse associated with such interval, depending upon whether said frequency wif is above or below said frequency wif .
 3. Apparatus in accordance with claim 1 in which said means for applying includes means for averaging said error control signal.
 4. Apparatus in accordance with claim 1 in which said differential phase detector means comprises: delay means responsive to said down converted signal for producing a delayed signal which is a replica of said down converted signal and which is delayed by T seconds relative thereto; and comparator means for comparing the phases of said delayed signal and said down converted signal.
 5. Apparatus in accordance with claim 1 in which said first and second phase differences are 0* and 180*, respectively.
 6. Apparatus in accordance with claim 1 in which said quadrature detector means comrpises: a delay means responsive to said down converted signal for generating a quadrature delayed signal which is a replica of said down-converted signal and which is delayed by T seconds plus 90* relative thereto; and means for comparing the phases of said quadrature delayed signal and said down converted signal.
 7. Apparatus in accordance with claim 1 in which said quadrature detector comprises: first and second hybrid couplers, each having first, second, third, and fourth ports, said first port of said first coupler being responsive to said down converted signal and said second port of said first coupler being connected to said first port of said second coupler; a delay means for providing a T second plus 90* delay to signals passing therethrough, said delay means being connected between said third port of said first coupler and fourth port of said second coupler; a difference circuit whose output comprises said output signal, said difference circuit having first and second input ports; a first envelope detector connected between said second port of said second coupler and said first input port; and a second envelope detector connected between said third port of said second coupler and said second input port.
 8. Apparatus in accordance with claim 7 in which each of said couplers is a 3db hybrid coupler.
 9. Apparatus in accordance with claim 7 in which a signal applied to the first port of each of said couplers is equally divided between said second and third ports thereof, with the portion of the signal appearing at the second port receiving a 0* relative phase shift and the portion appearing at the third port a 90* relative phase-shift; and a signal applied to the fourth port of each of said couplers is equally divided between said second and third ports thereof, with the portion of the signal appearing at the third port receiving a 0* relative phase shift and the portion appearing at the second port a 180* relative phase-shift.
 10. Apparatus in accordance with claim 1 in which said output signal is of substantially the opposite polarity to said binary signal when wif is above wif and is of substantially the same polarity as said binary signal when wif is below wif .
 11. Apparatus in accordance with claim 8 in which said error control signal is of substantially a negative polarity when wif is above wif and said error control signal is of substantially a positive polarity when wif is below Wif . 